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Release Notes for StellarisWare Revision 5961 (May 3, 2010)

11.2.2 The USB Host Pipe Read/Write functions improperly handle STALL

(Reference 12024)

The USBHCDPipeWrite() and USBHCDPipeRead() functions both failed to handle stall conditions

on endpoints other than zero. This caused the USB library to falsely enter the status phase when it

should have terminated the stalled transaction.

11.2.3 USBOTGModeInit() causes ASSERT in debug builds (Reference

12030)

The USBOTGModeInit() function called the USBHostPwrConﬁg() DriverLib API with bits set that did

not have meaning in the USBHostPwrConﬁg() API which caused it to ASSERT and halt in debug

builds. The USBHostPwrConﬁg() has been replaced with a call to a new API USBHCDPowerCon-

ﬁgSet() which correctly sets the power conﬁguration.

11.3 Bug Fixes in DK-LM3S9B96 Firmware Package

11.3.1 Hang in qs-checkout if run with FS8 daughter containing non-

ﬁlesystem image (Reference 11976)

The qs-checkout example application could hang if run on a board equipped with the

Flash/SRAM/LCD daughter board where the daughter board ﬂash contained data other than a

valid ﬁle system image. The application now correctly checks for a valid ﬁle system image header

before trying to access the data.

11.3.2 Internal pull-ups removed from EPI pin conﬁguration (Reference

12019)

The conﬁguration used for each Extended Peripheral Interface pin in set_pinout.c has been

changed to remove the internal weak pull-ups since these are not required.

11.3.3 FPGA daughter board initialization problem on power-on-reset (Ref-

erence 12034)

In the previous code release, the FPGA/Camera/LCD daughter board would often not initialize cor-

rectly after a power-on-reset, requir ing the user to press the “Reset” button to restart the application.

This problem is due to the fact that the FPGA is conﬁgured to pull unconﬁgured pins up rather than

down. The ready signal on PJ6/EPI30 was a low to high transition on one of those pins so this was

masked by the fact that the pin was already high. To work around the problem, the initialization

code no longer polls PJ6 looking for a rising edge but, instead, delays 600mS after resetting the

FPGA and before accessing any of its registers.

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